Abstract: As a fullsystem simulation technology allowing one to completely simulate the functionality of computer systems with different memory hierarchy configurations and different number of processors, Vitutech Simics has an inorder ‘flat’ cache model which only provides with a simple snooping cache coherence protocol support for a simple MESI protocol between caches with a unified shared memory. This limits the number of processors that can be scalable to simulate for the logical bus contention. This paper presents a simple distributed directorybased cache coherence protocol that will solve scalability problem of Simics.

Key words: computer simulation, Simics, chip multiprocessor, cache coherence protocol, directorybased cache coherence protocol